1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of semiconductor devices, and, more specifically, to a novel fin cutting process for manufacturing FinFET semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each transistor device comprises laterally spaced apart drain and source regions that are formed in a semiconductor substrate, a gate electrode structure positioned above the substrate and between the source/drain regions, and a gate insulation layer positioned between the gate electrode and the substrate. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region and current flows from the source region to the drain region.
A conventional FET is a planar device wherein the entire channel region of the device is formed parallel and slightly below the planar upper surface of the semiconducting substrate. In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 wherein the fins 14 of the device 10 are made of the material of the substrate 12, e.g., silicon. The device 10 includes a plurality of fin-formation trenches 13, three illustrative fins 14, a gate structure 16, a sidewall spacer 18 and a gate cap layer 20. An insulating material 17 (with an upper surface 17S) provides electrical isolation between the fins 14. The gate structure 16 is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers that serve as the gate electrode for the device 10. The fins 14 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational, i.e., it corresponds to the gate length direction of the device. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. The portions of the fins 14 that are positioned outside of the spacers 18 will become part of the source/drain regions of the device 10.
In the FinFET device 10, the gate structure 16 encloses both sides and the upper surface of the fins 14 to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fins 14 and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, a FinFET device typically exhibits the improved gate control, thereby reducing so-called short channel effects that occurred on planar devices with very small gate lengths. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
As FinFET devices have been scaled to meet ever increasing performance and size requirements, the desired final lateral width of the fins 14 (near the top of the fin) has become very small, e.g., 6-12 nm, and the fin pitch has also been significantly decreased, e.g., the fin pitch may be on the order of about 30-60 nm. Moreover, after the fins 14 are initially formed, they will be subjected to various processing operations, e.g., cleaning, growth of thermal oxide material on the fins 14 that act to consume some of the lateral width (and height) of the initially formed fins. Accordingly, accurately defining these relatively small fin structures 14 while accounting for their subsequent reduction in size in post fin-formation processes can be challenging. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form a patterned fin-formation etch mask layer (not shown) that is comprised of a plurality of spaced-apart line-type features (that correspond to the desired fins) above the substrate 12. Thereafter, one or more etching processes are performed though the patterned fin-formation etch mask layer to define the fin-formation trenches 13 in the substrate 12 that defines a regular array of multiple fins 14 that extend across the entire substrate 12. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins 14 to very small dimensions due to the more uniform environment in which the etching process that forms the fin-formation trenches 13 is performed.
However, when manufacturing FinFET devices, spaces for isolation structures must be provided between FinFET devices on the final integrated circuit product. One prior art processing technique that is performed to provide for these isolation spaces is sometimes referred to as a “Fin-Cut-Last” process. In the Fin-Cut-Last process, after the fin-formation trenches 13 have been formed so as to thereby define the regular array of fins 14 across the substrate 12, some portion or portions of several fins 14 are removed to create room for or define the spaces where isolation regions will ultimately be formed to separate the individual FinFET devices from one another.
Another prior art processing technique that is performed to form the spaces for the isolation structures is sometimes referred to as a “Fin-Cut-First” process. In general, the term “Fin-Cut-First” to describe the process is a bit of a misnomer in that, using this Fin-Cut-First technique, the portions of the “fins” to be removed are not actually formed in the substrate 12. Rather, in the Fin-Cut-First process, some portions of the line-type features in the patterned fin-formation etch mask layer are removed prior to performing the etching process that defines the fins 14 in the substrate 12. Accordingly, when the fin-formation etching process is performed through the modified patterned fin-formation etch mask layer (with some portions of the line type features removed) to define the fins 14, no fins 14 will form in the locations corresponding to the removed line-type features from the original patterned fin-formation etch mask layer. The spaces created where the fins 14 are not formed are the spaces where isolation regions will be formed.
However, as fin widths and fin pitches continue to decrease, the Fin-Cut-First process is becoming more challenging, as will be explained with reference to FIGS. 1B-1H. FIG. 1B depicts a product after an initial patterned fin-formation hard mask layer 30, e.g., a patterned layer of silicon nitride/silicon dioxide, was formed above the substrate 12 in accordance with the desired fin pattern and pitch. The patterned fin-formation hard mask layer 30 is comprised of a plurality of line-type features 30A that extend across the substrate 12 (the features 30A extend into and out of the plane of the drawing page). Also depicted in dashed lines are illustrative fins 14 that will eventually be formed in the substrate 12 by performing an etching process through the patterned fin-formation hard mask layer 30 after portions of some of the line-type features 30A have been removed.
Some problems with such a prior art Fin-Cut-First manufacturing technique are best explained with an illustrative numerical example. For example, the fins 14 may have a target width 14W (at the top of the fin) at this point in the process flow (with the understanding that the width 14W will be reduced in subsequent manufacturing operations) of about 16 nm, and they may be formed with a desired fin pitch 14P of 30 nm. The line-type features 30A are formed so as to have a lateral width 30W that is slightly larger (e.g., 18 nm) than the target width 14W of the fins 14 to account for the natural size reduction of the fin 14 when the fin-formation etching process is performed. As a result of these constraints, the lateral space 32 between adjacent line-type features 30A may be about 12 nm.
FIGS. 1C-1D depict the formation of a patterned etch mask layer 40, i.e., a so-called fin-cut mask, above the patterned fin-formation hard mask layer 30. The patterned etch mask 40 may be made of any desired materials and it may be formed using traditional photolithographic tools and techniques. The patterned etch mask 40 has an opening 40A that exposes portions 30X of three of the line-type features 30A that are to be removed from the patterned fin-formation hard mask layer 30 to define a modified fin-formation etch mask layer 30 (with the portions 30X removed). The opening 40A has a target lateral width 40W. Ultimately, an etching process will be performed through the modified fin-formation hard mask layer 30 to define the fins 14 in the substrate 12.
In the example depicted in FIGS. 1C-1D, the opening 40A is depicted as being formed precisely to its targeted width 40W and with its edges 40X being perfectly aligned and positioned in the middle of the 12 nm lateral space 32 between adjacent features 30A. Unfortunately, accurately and reliably forming the opening 40A to its target width 40X and/or locating the edges 40X of the opening 40A this precisely is very difficult to accomplish in practice. Given that the lateral space 32 is about 12 nm (in the example described), that means there is only a tolerance or process window of about plus-or-minus 6 nm when it comes to defining the width 40W of the opening 40A precisely and/or to accurately locating the edges 40X of the opening 40A at the proper location between adjacent features 30A. If the mask opening 40A is not properly sized and/or located, problems can result, as described more fully below.
In the example depicted in FIGS. 1E-1F, the opening 40A is depicted as being formed with a lateral width 40W1 that is greater than its targeted width 40W. As depicted, the over-sized opening 40A exposes portions 42 of certain line features 30A that, according to the design process, should not be removed. If the exposed portions 42 are removed, then the fins that should have been formed under these exposed and removed portions 42 will not be formed, or at least not to the desired targeted width 14W. In the example depicted in FIGS. 1G-1H, the opening 40A is depicted as being formed with a lateral width 40W2 that is less than its targeted width 40W. As depicted, the undersized opening 40A covers portions 44 of line features 30A that, according to the design process, should be removed. If the covered portions 44 are not removed, then fins or partial fins will be formed in areas where they should not be formed. Even if the opening 40A in the etch mask 40 is formed to exactly match the target width 40W, properly aligning such a perfectly-sized opening is still a very challenging task given the very small process window (e.g., +/−6 nm) that must be met.
The present disclosure is directed to a novel fin cutting process for manufacturing FinFET semiconductor devices that may solve or reduce one or more of the problems identified above.